`timescale 1ns / 1ns

module led_shifting_tb;

    reg clk, rst_n, left_cmd, right_cmd, s_p;
    wire [7:0] led;

    initial begin
        $dumpfile("output/led_shifting_tb.vcd");
        $dumpvars(0, led_shifting_tb);
    end

    initial begin
        clk = 0;
        rst_n = 0;
        left_cmd = 1;
        right_cmd = 0;
        s_p = 0;

        #100 rst_n = 1;
        #100 s_p = 1;
        #20 s_p = 0;
        #100 s_p = 1;
        #20 s_p = 0;
        #100 s_p = 1;
        #20 s_p = 0;
        #100 s_p = 1;
        #20 s_p = 0;
        left_cmd = 0;
        right_cmd = 1;
        #100 s_p = 1;
        #20 s_p = 0;
        #100 s_p = 1;
        #20 s_p = 0;
        #100 s_p = 1;
        #20 s_p = 0;
        #100 s_p = 1;
        #20 s_p = 0;
        #100 s_p = 1;
        #20 s_p = 0;

        #100 $stop;
    end

    always #10 clk = ~clk;

    led_shifting led_shifting_inst (
        .clk                    (clk),
        .rst_n                  (rst_n),
        .left_cmd               (left_cmd),
        .right_cmd              (right_cmd),
        .s_p                    (s_p),
        .led                    (led)
    );

endmodule  //led_shifting_tb